Multi-layer thin film high density interconnect structures for interconnecting integrated circuit chips provide many apparent advantages to the electrical circuit designer. The high density interconnects provide very tight packaging of the circuit chips with shorter external conductor paths and resultant improvements in signal path speeds. However, as interconnect path densities increase at the substrate, difficulties arise in conducting heat generated within the integrated circuit chip during its operation to the substrate (or to a metal plane formed on the substrate) from which it may then be carried away or dissipated by a heat sink, etc.
High density interconnects are multi-layer, very fine feature printed circuit boards which are typically fabricated by using techniques employed in the manufacture of the integrated circuit chips themselves. In one typical arrangement, the interconnect structure will include a substrate of thin film ceramic, crystalline silicon, or metal upon which multiple layers of thin film conductors are formed. The conductors within a particular layer, and the conductors from layer to layer, are separated by a polymer dielectric, such as polyimide. A continuous ground plane layer of metal is typically deposited onto a planarized thin film substrate.
Following formation of the metal ground plane layer, alternating layers of polymer dielectric and thin film metal conductors are laid down (typically forming e.g. x-dimension signal plane layer, y-dimension signal plane layer, power plane layer and top metal layer). The metal conductors are conventionally patterned with photolithographic techniques including applying a metal plane, and then applying, patterning and developing a photoresist in order to pattern the metal plane.
One increasingly popular form of high density interconnect structure is known as a multichip module. A multichip module is one form of hybrid circuit and comprises a single substrate to which two or more integrated circuit chips are mounted and interconnected. In order to minimize the size of the module, it is desirable to mount the circuit chips on top of the multilayered support substrate in a manner wherein at least some of the signal and power paths lie under the chips.
In many multichip module applications heat generated by the integrated circuit chips is conducted out to and through the thin film substrate. The substrate also supports a multilayer structure which provides the electrical signals and power. This particular heat and electrical flow arrangement presents a difficult and hitherto costly challenge to the multichip module designer because of the nature of the dielectric insulation that is used to isolate the interconnect path conductors. In most prevalent multichip module applications a polymer such as polyimide is used as the insulating dielectric. Unfortunately, polymers are very poor thermal conductors.
It is essential to remove heat from operating integrated circuit chips in order to prevent chip feature and to maintain and extend the lifetime of these devices. In many multichip module applications, high signal routing densities in the multiple layers underneath the chip block the heat path between the chip and the substrate. If thermal conductor paths are provided through the multilayer interconnect to the substrate in order to provide requisite heat transfer through the non-conductive polyimide layers, these thermal conductor paths necessarily limit the signal routing channels otherwise available for conductive paths directly under the chip from which heat is being transferred.
Thermal vias are typically used to conduct heat through the insulative layers of the high density interconnect directly under the integrated circuit chip. The effectiveness of a thermal via is dependent in large measure upon the type of via employed for thermal conduction. In turn, the thermal via is dependent upon the processing method employed to fabricate the multilayer thin film interconnect structure.
There are two general types of fabrication processes which have been used to form vias, whether for thermal or electrical conduction (or both), in high density interconnect layers: staggered conformal vias, and thermal post plate-up vias formed on an iterative (step-by-step) basis with a number of separate process steps occurring at each metal layer of the multilayer structure. Both processes have employed plural steps at each layer which are repeated at the next layer, and so on. Thus, these prior processes are referred to herein as "iterative" processes.
The staggered conformal vias method relies upon patterning holes in the dielectric layer, followed by a metallization step over the exposed and patterned substrate and down into the dielectric holes to make the vertical interconnections or vias between adjacent metal layers. The vias formed by this process are conformal or "cup-like". These vias are conventionally used for electrical conduction, and they have likewise been used for thermal conduction as well.
FIGS. 1 and 2 illustrate in greatly enlarged, highly diagrammatic views a five conductor layer high density interconnect structure 10 formed in accordance with the prior art. The structure 10 includes a thin film substrate 12 which may be of ceramic, semiconductor grade crystalline silicon, or metal. A thin film ceramic substrate 12 is shown in FIG. 1. Alternating layers of polymer dielectric and metal conductors are formed on the substrate 12. There are five such layers shown in FIG. 1: a ground plane layer 14 formed directly upon the substrate 12, an X-dimension signals layer 16 above the ground plane 14, a y-dimension signals layer 18 above the X-dimension signals layer 16, a power plane layer 20, and a top metal layer 22. A thermally conductive cured epoxy layer 24 secures a semiconductor integrated circuit chip 26 to the top metal layer 22.
As outlined in the FIG. 3 process flowchart, a multilayer staggered conformal via formation 28 may be formed iteratively to provide a thermal conductor path from the chip 26 downwardly through each metal layer 22, 20 18, 16, 14 to the substrate 12. The metal layers are typically defined by the steps of depositing a thin film metal layer e.g. by sputter deposition, at a step 11. A resist layer is then coated (e.g. by spin coating) at a step 13. The coated resist is then exposed (patterned) at a step 15 and developed at a step 17 to expose portions of the metal layer to be removed. The metal layer is then patterned by etching e.g. with a wet chemical etch at a step 19, after which the resist residue is removed at a step 21. A subsequent layer of dielectric is then deposited at a step 23. Via openings are defined in the newly deposited layer at a step 25, and this process is then reiterated for the next metal layer at the step 11.
Each metal layer is separated by a polymer dielectric which has been coated (e.g. by spin coating) and cured. Interconnections between the layers are thus accomplished by forming cup like conformal vias 30, 32 and 34, as described hereinabove. A principal drawback of the FIGS. 1-3 approach for thermally connecting the chip 26 to the substrate 12 through the formation 28 is that the formation 28 is staggered; i,e, it requires considerable space at each metal layer in order to provide for a staggered connection to the layer above it, and to the layer below it, thereby encroaching into otherwise available routing channel space under the chip 26.
FIG. 4 illustrates in cross section and greatly enlarged elevational view another typical five layer high density structure like the structure 10 shown in FIG. 1, except that a planarizing layer 27 of coated polymer material is placed on the substrate 12 and further thermally isolates it from the chip 26. In this example, no metal conductor direct thermal paths are provided from the chip 26 to the substrate 12, and this prior approach accordingly represents a least desired approach for transferring heat from the chip 26 to the substrate 12.
In the prior art cooling methods, heat from a multichip module is typically dissipated to the ambient by a convection heat sink 36 attached to the underside of the substrate 12. One prior approach to improve thermal conductivity between the chip 26 and the ambient is simply to define a well 40 through a high density interconnect structure 42 to enable the integrated circuit die 26 to be mounted in direct thermal contact with a heat sink 36, as shown in FIG. 5. It is manifestly evident that the drawback presented by the FIG. 5 approach is the total elimination of any conductive layer routing channel paths extending directly beneath the chip 26. With the FIG. 5 approach, all of the signal and power paths must be routed completely around the well 40, thereby greatly extending the required size of the multi-chip module 42 for a given number of interconnect paths.
Another approach found in the prior art is to provide a thermal well extending through all of the high density interconnect metal and dielectric layers to the substrate 12. This approach is illustrated in FIG. 6 wherein the high density interconnect layers 44 are interrupted by a well 46 which extends to the substrate 12. In this prior example, the integrated circuit chip or die 26 is mounted in the well 46. As with the FIG. 5 approach, the FIG. 6 approach eliminates all interconnects from being directly under the chip 26 and likewise requires a much larger multi-chip module for a given functionality.
A high density interconnect 44 defining a partial thermal well 48 is shown in FIG. 7. In this approach, the integrated circuit chip 26 is attached to the power plane layer 20 by a thermally conductive epoxy layer 24. While moderate heat loads may be transferred to the substrate by thermal conduction, heat transfer remains inefficient with this approach.
The FIG. 8 plan view illustrates a prior approach employing via island arrays 50 of blind staggered thermal conduction vias, such as the via structure 28 of FIGS. 1 and 2. These arrays 50 provide some further improvement in heat transfer between the chip 26 and the substrate 12 while leaving some room for conductive traces at the X-dimension level 16 and y-dimension level 18. However, the fact that the thermal path of each structure 28 is staggered from layer to layer limits the practical density of the vias within the island arrays 50 and therefore the amount of heat that may be conducted directly to the substrate.
While staggered conformal vias are conventionally used to provide interlayer electrical and thermal conduction paths, greater thermal efficiency has resulted from plating up the vias to form a solid metal thermal post which transfers heat directly between the chip and the substrate. Accordingly, the second or post-plate-up vias method relies upon e.g. an iterative electroplating process in order to plate up conductors as solid posts at locations defined by a temporary photoresist pattern at each layer. The problem with forming post-plate-up vias on a step by basis is that this process requires a number of separate steps at each layer.
To elaborate, in forming a post at a particular layer a metallization planar layer is formed. The metallization layer is then coated with a photoresist. The photoresist is then patterned and selectively removed along with the underlying metal, leaving metal post plateus. A polyimide is then coated onto the structure to fill in the voids between the metal post plateaus, and usually overcoats the plateaus as well. Any overcoat must then be removed by micromachining techniques, such as a lapping process which removes several microns of the polyimide overcoat, or a gross plasma etch system which burns off a requisite depth of the polyimide overcoat. Irrespective of the removal technique, the top surface of the metal post must be exposed before the next layer may be formed by plating-up from that surface.
These iterative post plate-up steps are summarized in FIG. 9. The iterative post via process of the prior art begins at each metal layer with a metal deposition step 31. A photoresist is then coated onto the metal layer at a step 33. The resist is then selectively exposed to light energy at a step 35, and developed chemically at a step 37. Metal is then plated upon the developed resist at a step 39. Resist is then coated upon plated metal at a step 41 and exposed at a step 43. The resist is then developed at a step 45, and an increment of the metal post is plated at a step 47. The resist is then stripped away at a step 49. The field metal is then etched away at an etch step 51. Dielectric is then coated onto the resultant structure at a step 53, and is then lapped or etched at a step 55. This process then repeats at the next metal layer to be defined.
The prior layer-by-layer process steps, while effective in forming vertical posts, are very time consuming and expensive. However, from a thermal conductivity point of view, the solid thermal post via is superior in performance to the conformal via, due to the direct thermal path available to conduct the heat away from the semiconductor die and through to the substrate (or to a metal plane adjacent to the substrate). The superior thermal conductivity of the solid post via permits higher routing channel densities under the chip without sacrificing thermal performance of the high density interconnect structure. Yet the drawback of this prior approach, namely the complexity, time and costs associated with the additional process steps required to form the solid post thermal vias, limits its attractiveness as an approach for realization of a low cost high density interconnect structure.